Amplificateur | Condensateur | Electronique | Oscilloscope | Résistance | ||||
Circuit imprimé | Diode | Microprocesseur | Pile | Semi-conducteur | ||||
Circuit intégré | Fréquence | Moteur | Redressement | Transistor | ||||
Texas Instrument |
INTRODUCTION
These symbols, terms, and definitions are in accordance with
those currently agreed upon by the JEDEC Council of the Electronic Industries
Association (EIA) for use in the USA and by the International Electrotechnical
Commission (IEC) for international use.
operating conditions and characteristics (in sequence by letter symbols)
Ci Input capacitance The internal capacitance
at an input of the device
Cio Input/output capacitance Input–to–output
internal capacitance; transcapacitance
Co Output capacitance The internal capacitance
at an output of the device
Cpd Power dissipation capacitance Used to
determine the no–load dynamic power dissipation per logic function (see individual
circuit pages): PD = Cpd· VCC^2·f+ICC·VCC
fmax Maximum clock frequency The highest
rate at which the clock input of a bistable circuit can be driven through its
required sequence while maintaining stable transitions of logic level at the
output with input conditions established that should cause changes of output
logic level in accordance with the specification
ICC Supply current
The current into* the VCC supply terminal of an integrated circuit
DIcc
Supply current change The increase in supply current for each input that
is at one of the specified TTL voltage levels rather than 0 V or VCC
ICEX Output high leakage
current The maximum leakage current into the collector of the pulldown
output transistor when the output is high and the output forcing condition VO
= 5.5 V
II(hold) Input hold current
Input current that holds the input at the previous state when the driving
device goes to a high–impedance state
IIH High–level input current
The current into* an input when a high–level voltage is applied to that
input
IIL Low–level input current
The current into* an input when a low–level voltage is applied to that
input
Ioff Input/output power–off
leakage current The current into a circuit mode when the device or a
portion of the device affecting that circuit node is in the off state
IOH High–level output current
The current into* an output with input conditions applied that, according
to the product specification, establish a high level at the output
IOL Low–level output current
The current into* an output with input conditions applied that, according
to the product specification, establish a low level at the output
IOZ IOZPU/PD Off–state (high–impedance–state)
output current (of a 3–state output) The current flowing into* an output
having 3–state capability with input conditions established that, according
to the product specification, establish the high–impedance state at the output
RqJA
Junction–to–ambient thermal resistance The thermal resistance from the
semiconductor junction(s) to the ambient
RqJC
Junction–to–case thermal resistance The thermal resistance from the semiconductor
junction(s) to a stated location on the case
ta Access time The
time interval between the application of a specified input pulse and the availability
of valid signals at an output
tc Clock cycle time
Clock cycle time is 1/fmax
tdis Disable
time (of a 3–state or open–collector output) The propagation time between
the specified reference points on the input and output voltage waveforms with
the output changing from either of the defined active levels (high or low) to
a high–impedance (off) stateNOTE: For 3–state outputs, tdis = tPHZ or tPLZ Open–collector
outputs change only if they are low at the time of disabling, so tdis = tPLH
ten Enable time (of a 3–state
or open–collector output) The propagation time between the specified
reference points on the input and output voltage waveforms with the output changing
from a high–impedance (off) state to either of the defined active levels (high
or low)NOTE: In the case of memories, this is the access time from an enable
input (e.g., OE). For 3–state outputs, ten = tPZH or tPZL. Open–collector outputs
change only if they are responding to data that would cause the output to go
low, so ten = tPHL
th Hold time The
time interval during which a signal is retained at a specified input terminal
after an active transition occurs at another specified input terminal
NOTES:
1. The hold time is the actual time interval between two signal events and is
determined by the system in which the digital circuit operates. A minimum value
is specified that is the shortest interval for which correct operation of the
digital circuit is to be expected.
2. The hold time may have a negative value in which case the minimum limit defines
the longest interval (between the release of the signal and the active transition)
for which correct operation of the digital circuit is to be expected.
tpd Propagation delay time
The time between the specified reference points on the input and output
voltage waveforms with the output changing from one defined level (high or low)
to the other defined level (tpd = tPHL or tPLH)
tPHL Propagation delay time,
high–to–low level output The time between the specified reference points
on the input and output voltage waveforms with the output changing from the
defined high level to the defined low level
tPHZ Disable time (of a
3–state output) from high level The time interval between the specified
reference points on the input and the output voltage waveforms with the 3–state
output changing from the defined high level to the high–impedance (off) state
tPLH Propagation delay time,
low–to–high level output The time between the specified reference points
on the input and output voltage waveforms with the output changing from the
defined low level to the defined high level
tPLZ Disable time (of a
3–state output) from low level The time interval between the specified
reference points on the input and the output voltage waveforms with the 3–state
output changing from the defined low level to the high–impedance (off) state
tPZH Enable time (of a 3–state
output) to high level The time interval between the specified reference
points on the input and output voltage waveforms with the 3–state output changing
from the high–impedance (off) state to the defined high level
tPZL Enable time (of a 3–state
output) to low level The time interval between the specified reference
points on the input and output voltage waveforms with the 3–state output changing
from the high–impedance (off) state to the defined low level
tsk(o) Output Skew
The difference between any two propagation delay times when a single switching
input or multiple inputs switching simultaneously cause multiple outputs to
switch, as observed across all switching output. This parameter is used to describe
the fanout capability of a clock driver and is of concern when making decisions
on clock buffering and distribution networks tsu Setup time The time
interval between the application of a signal at a specified input terminal and
a subsequent active transition at another specified input terminal
NOTES:
1. The setup time is the actual time interval between two signal events and
is determined by the system in which the digital circuit operates. A minimum
value is specified that is the shortest interval for which correct operation
of the digital circuit is guaranteed.
2. The setup time may have a negative value, in which case the minimum limit
defines the longest interval (between the active transition and the application
of the other signal) for which correct operation of the digital circuit is guaranteed.
tw Pulse duration (width) The time interval between specified
reference points on the leading and trailing edges of the pulse waveform
VIH High–level
input voltage An input voltage within the more positive (less negative)
of the two ranges of values used to represent the binary variables
NOTE: A minimum is specified that is the least–positive value
of high–level input voltage for which operation of the logic element within
specification limits is to be expected.
VIL Low–level input voltage
An input voltage within the less positive (more negative) of the two
ranges of values used to represent the binary variables
NOTE: A maximum is specified that is the most–positive value
of low–level input voltage for which operation of the logic element within specification
limits is to be expected.
VOH High–level
output voltage The voltage at an output terminal with input conditions
applied that, according to product specification, establish a high level at
the output
VOL Low–level output voltage
The voltage at an output terminal with input conditions applied that,
according to product specification, establish a low level at the output
VIT+ Positive–going input
threshold level The voltage level at a transition–operated input that
causes operation of the logic element according to specification as the input
voltage rises from a level below the negative–going threshold voltage,
VIT- Negative–going input
threshold level The voltage level at a transition–operated input that
causes operation of the logic element according to specification as the input
voltage falls from a level above the positive–going threshold voltage,
VIT+ VOHV High–level output
voltage change during simultaneous switching The minimum (valley) voltage
induced on a quiescent high–level output during switching of other outputs
VOLP Low–level output voltage
change during simultaneous switching The maximum (peak) voltage induced
on a quiescent low–level output during switching of other outputs
Definitions
asynchronous FIFO
Data writes are initiated by a low–level pulse on
the write–enable input when the full flag is not asserted. Likewise, data
reads are initiated by a low–level pulse on the read–enable input when
the empty flag is not asserted. The empty and full flags are not synchronized
to a particular clock and reflect the instantaneous comparison of the read
and write pointers.
clocked FIFO
Data is written by a low–to–high transition of a write clock
when write–enable inputs are asserted and the input–ready flag is not asserted.
Likewise, data is read by a low–to–high transition of a read clock when read–enable
inputs are asserted and the output–ready flag is asserted. The input–ready flag
is multistaged synchronized to the write clock and the ouput–ready flag is multistaged
synchronized to the read clock, improving metastability.
strobed FIFO
Data is written on a low–to–high transition on the load–clock
input when the full flag is not asserted. Likewise, data is read on a low–to–high
transition on the unload–clock input when the empty–flag is not asserted. The
empty and full flags are not synchronized to a particular clock and reflect
the instantaneous comparison of the read and write pointers.
synchronous FIFO
The term synchronous refers to a port–control method
and does not imply that data writes and reads must be synchronous to one
another.
Data is written by a low–to–high transition of a
write clock when write–enable inputs are asserted and the full flag is
not asserted. Likewise, data is read by a low–to–high transition of a read
clock when read–enable inputs are asserted and the empty flag is not asserted.
The empty flag is single–staged synchronized to the read clock and the
full flag is single–staged synchronized to the write clock.