The following sections detail the conventions used in this manual.

• Text Conventions
• White Characters
• Naming Variables
• Constants Defined
• Character Set

The following table details the special characters and markings used in this manual.

Convention Meaning

Bold Menu names and commands.

Italics Text you type. Names are case insensitive.

White characters (including blanks, tabs, and new line characters) are used to separate text strings. There is a special standard for entering the tab character, as this key is used for other purposes in dialog boxes and menus.

Character Key(s)

Names start with an alphabetic character and may be up to sixteen characters long. The last character must be an alpha-numeric (A..Z, a..z, 0..9). The remaining characters may include alpha-numeric and the underscores. Only single underscores may be used - double underscores are flagged as errors. Names are not case sensitive. Names of signals may be up to 16 characters long, and names of vectors can be up to 14 characters. The following are examples of valid names:

Constants may be used with the inequality operators for the purposes of comparing vectors. The constants may be defined in bases 2, 8, 10 or 16. Decimal (base 10) is used when no base specifier is given. A constant may be specified as a numeric value or as a base specifier followed by a constant value. Binary constants may also be defined using VHDL syntax. Single bit constants are enclosed in single quotes, multiple bit constants are enclosed in double quotes. To explicitly indicate a base, the caret symbol '^' followed by a base specifier character is used:

Example of valid constants are:

Spaces and other characters are not allowed in constants. Only characters for the specified radix are allowed in the constant.

Examples of invalid constants:

Predefined constants provide a way to insure a condition is always true or to strap a signal. These operators are not case sensitive. They may be used in equations in the same manner as variables.

StateCAD allows the definition of variables names, constants, boolean equations and comments. The following tables define the characters and their usage:

• StateCAD Character Set
• Logic Operators
• Inequality Operators
• Addition / Subtraction
• VHDL Statements

The following table lists the characters used in names, comments, and equations.

The following table lists the valid boolean logic operators. Inequalities are listed in the following table:

Inequalities are supported between vectors and constants and yield a boolean (single bit) result. Inequalities can be used in both bit equations and vector equations. When inequalities are used in equations, the resulting bit logic is expanded to the destination vector's width. The operators listed below detail these operators. Many of these operators consist of two characters.

Vector equations can include logical operations (and / or / complement) as well as inequalities, bit logic (such as bus muxing), and adding (or subtracting) vectors (or constants). Addition (and subtraction) operations require parenthesis around the operands. Also, addition (and subtraction) operations can only occur on vector variables (and constants), you can not use equations as operands. Use of addition allows for counters (i.e. COUNT=COUNT+1) in outputs (state and transition) and logic equations. Also, using addition you can create ALUs, and other complex functions.

When using manual output optimization, vectors equations which utilize addition (or subtraction) can be assigned as registered even when other outputs default to combinatorial (see "Clock Counters").

A subset of standard VHDL 1076 (and OVI Verilog) statements may be used in conditions and outputs, allowing diagrams to be drawn using either VHDL, Verilog, or ABEL-HDL type logic. ABEL-HDL, Altera-HDL, Verilog, and VHDL logic formats may be mixed when convenient. Supported VHDL output operators are:

Supported Verilog operators are &, |, !, and the = for assignment..

Supported operations for conditions are the equality operators (=, /=, <. ,<=, >, >=), logic operators (AND, OR, NOT), and the binary constants (1 and 0 only) (i.e. "100" is binary 4). Bit and vector comparisons are supported. Note: Bit='0' is supported, but '0'=Bit is not supported.

Conditions and single bit assignments must have equations (or constants) which yield single bit results. Vector outputs must be assigned equations with vector results, however bit comparisons / muxing are automatically expanded to the vectors width.

Example of equivalent statements include:

VHDL Syntax